fw1.0 SHT:ok(0/0) BMP:ok(0/0) i2c:45,77 rec:0 up:2853/1 rst:Power On
2026-10-26 16:06:55 UTC
fw1.0 SHT:ok(0/0) BMP:ok(0/0) i2c:45,77 rec:0 up:2852/1 rst:Power On
2026-10-26 16:05:55 UTC
fw1.0 SHT:ok(0/0) BMP:ok(0/0) i2c:45,77 rec:0 up:2851/1 rst:Power On
2026-10-26 16:04:55 UTC
fw1.0 SHT:ok(0/0) BMP:ok(0/0) i2c:45,77 rec:0 up:2850/1 rst:Power On
2026-10-26 16:03:55 UTC
fw1.0 SHT:ok(0/0) BMP:ok(0/0) i2c:45,77 rec:0 up:2849/1 rst:Power On
2026-10-26 16:02:55 UTC
fw1.0 SHT:ok(0/0) BMP:ok(0/0) i2c:45,77 rec:0 up:2848/1 rst:Power On
2026-10-26 16:01:55 UTC
fw1.0 SHT:ok(0/0) BMP:ok(0/0) i2c:45,77 rec:0 up:2847/1 rst:Power On
2026-10-26 16:00:55 UTC
fw1.0 SHT:ok(0/0) BMP:ok(0/0) i2c:45,77 rec:0 up:2846/1 rst:Power On
2026-10-26 15:59:55 UTC
fw1.0 SHT:ok(0/0) BMP:ok(0/0) i2c:45,77 rec:0 up:2845/1 rst:Power On
2026-10-26 15:58:55 UTC
fw1.0 SHT:ok(0/0) BMP:ok(0/0) i2c:45,77 rec:0 up:2844/1 rst:Power On
2026-10-26 15:57:55 UTC
fw1.0 SHT:ok(0/0) BMP:ok(0/0) i2c:45,77 rec:0 up:2843/1 rst:Power On
2026-10-26 15:56:55 UTC
fw1.0 SHT:ok(0/0) BMP:ok(0/0) i2c:45,77 rec:0 up:2842/1 rst:Power On
2026-10-26 15:55:55 UTC
fw1.0 SHT:ok(0/0) BMP:ok(0/0) i2c:45,77 rec:0 up:2841/1 rst:Power On
2026-10-26 15:54:55 UTC
fw1.0 SHT:ok(0/0) BMP:ok(0/0) i2c:45,77 rec:0 up:2840/1 rst:Power On
2026-10-26 15:53:55 UTC
fw1.0 SHT:ok(0/0) BMP:ok(0/0) i2c:45,77 rec:0 up:2839/1 rst:Power On
2026-10-26 15:52:55 UTC
fw1.0 SHT:ok(0/0) BMP:ok(0/0) i2c:45,77 rec:0 up:2838/1 rst:Power On
2026-10-26 15:51:55 UTC
fw1.0 SHT:ok(0/0) BMP:ok(0/0) i2c:45,77 rec:0 up:2837/1 rst:Power On
2026-10-26 15:50:55 UTC
fw1.0 SHT:ok(0/0) BMP:ok(0/0) i2c:45,77 rec:0 up:2836/1 rst:Power On
2026-10-26 15:49:55 UTC
fw1.0 SHT:ok(0/0) BMP:ok(0/0) i2c:45,77 rec:0 up:2835/1 rst:Power On
2026-10-26 15:48:55 UTC
fw1.0 SHT:ok(0/0) BMP:ok(0/0) i2c:45,77 rec:0 up:2834/1 rst:Power On
2026-10-26 15:47:55 UTC
fw1.0 SHT:ok(0/0) BMP:ok(0/0) i2c:45,77 rec:0 up:2833/1 rst:Power On
2026-10-26 15:46:54 UTC
fw1.0 SHT:ok(0/0) BMP:ok(0/0) i2c:45,77 rec:0 up:2832/1 rst:Power On
2026-10-26 15:45:54 UTC
fw1.0 SHT:ok(0/0) BMP:ok(0/0) i2c:45,77 rec:0 up:2831/1 rst:Power On
2026-10-26 15:44:54 UTC
fw1.0 SHT:ok(0/0) BMP:ok(0/0) i2c:45,77 rec:0 up:2830/1 rst:Power On
2026-10-26 15:43:54 UTC
fw1.0 SHT:ok(0/0) BMP:ok(0/0) i2c:45,77 rec:0 up:2829/1 rst:Power On
2026-10-26 15:42:54 UTC
fw1.0 SHT:ok(0/0) BMP:ok(0/0) i2c:45,77 rec:0 up:2828/1 rst:Power On
2026-10-26 15:41:54 UTC
fw1.0 SHT:ok(0/0) BMP:ok(0/0) i2c:45,77 rec:0 up:2827/1 rst:Power On
2026-10-26 15:40:54 UTC
fw1.0 SHT:ok(0/0) BMP:ok(0/0) i2c:45,77 rec:0 up:2826/1 rst:Power On
2026-10-26 15:39:54 UTC
fw1.0 SHT:ok(0/0) BMP:ok(0/0) i2c:45,77 rec:0 up:2825/1 rst:Power On
2026-10-26 15:38:54 UTC
fw1.0 SHT:ok(0/0) BMP:ok(0/0) i2c:45,77 rec:0 up:2824/1 rst:Power On
2026-10-26 15:37:54 UTC